1. Technical Field
The present invention generally relates to a semiconductor integrated circuit, and more particularly, to a bit line (BL) sense amplifier and a layout method therefor.
2. Related Art
In a semiconductor memory device, a BL sense amplifier is a circuit for amplifying a fine difference between signals that are generated in bit lines due to charge sharing between a memory cell and the bit lines after the memory cell is selected.
As the degree of integration of semiconductor devices increases, a BL sense amplifier has been developed from a folded bit line structure to an open bit line structure. The BL sense amplifier having the open bit line structure amplifies a difference between the signals of a pair of bit lines, extending from a memory cell block adjacent to the BL sense amplifier, using the bit lines as a primary bit line and a secondary bit line.
FIG. 1 shows the construction of a common BL sense amplifier and shows the construction of a 2-stage open BL sense amplifier.
In general, the BL sense amplifier can include a sense amplifier unit, a precharge and equalization unit, a column selection unit, etc. FIG. 1 shows only the sense amplifier unit.
Referring to FIG. 1, the sense amplifier unit of the BL sense amplifier includes a first sense amplifier 11 and a second sense amplifier 13.
The first sense amplifier unit 11 includes a first P type transistor P1 and a second P type transistor P2. The first P type transistor P1 has a source terminal connected to a power source voltage supply line CSP, a gate terminal connected to a bit line bar BLB, and a drain terminal connected to a bit line BL. The second P type transistor P2 has a source terminal connected to the power source voltage supply line CSP, a gate terminal connected to the bit line BL, and a drain terminal connected to the bit line bar BLB.
The second sense amplifier unit 13 includes a first N type transistor N1 and a second N type transistor N2. The first N type transistor N1 has a source terminal connected to a ground voltage supply line CSN, a gate terminal connected to the bit line bar BLB, and a drain terminal connected to the bit line BL. The second N type transistor N2 has a source terminal connected to the ground voltage supply line CSN, a gate terminal connected to the bit line BL, and a drain terminal connected to the bit line bar BLB.
Furthermore, the gate terminal of the first P type transistor P1 and the drain terminal of the second P type transistor P2 are coupled by a first lower line B1 that extends from a memory cell block to which the bit line bar BLB is connected. The gate terminal of the first N type transistor N1 and the drain terminal of the second N type transistor N2 are coupled by a second lower line B2 that extends from the memory cell block to which the bit line bar BLB is connected.
Furthermore, the gate terminal of the second P type transistor P2 and the drain terminal of the first P type transistor P1 are coupled by a first upper line T1 that extends from a memory cell block to which the bit line BL is connected. The gate terminal of the second N type transistor N2 and the drain terminal of the first N type transistor N1 are coupled by a second upper line T2 that extends from the memory cell block to which the bit line BL is connected.
FIGS. 2 and 3 are the layout diagrams of the common BL sense amplifier.
First, FIG. 2 shows a state in which the first and the second P type transistors P1 and P2 and the first and the second N type transistors N1 and N2 are formed over a semiconductor substrate. The transistors are formed using a similar method, and the second P type transistor P2 is described below as an example. An active region is defined in the semiconductor substrate, a gate G is formed, and a source S and a drain D are then formed by an ion implantation process, thereby being capable of forming the second P type transistor P2. A well pick-up region WP is a region for supplying a power source to the junction region S, D.
After forming a pair of the P type transistors P1 and P2 and a pair of the N type transistors N1 and N2 as shown in FIG. 2, the gate and drain terminals between each transistor is coupled by a line as shown in FIG. 3.
As described above, the gate terminal of the second P type transistor P2 and the drain terminal of the first P type transistor P1 are coupled by the first upper line T1. To this end, as shown in FIGS. 2 and 3, a process of forming a first contact C101, a process of forming a second contact C102 and a third contact C103, and a process of forming the first upper line T1 are performed.
Furthermore, in order to couple the gate terminal of the second N type transistor N2 and the drain terminal of the first N type transistor N1, fourth to sixth contacts C104, C105, and C106 are formed and electrically coupled by the second upper line T2.
Likewise, the gate terminal of the first P type transistor P1 and the drain terminal of the second P type transistor P2 are coupled by the first lower line B1. To this end, seventh to ninth contacts C107, C108, and C109 are used.
Furthermore, the gate terminal of the first N type transistor N1 and the drain terminal of the second N type transistor N2 are coupled by tenth to twelfth contacts C110, C111, and C112 and the second lower line B2.
If the BL sense amplifier is configured as described above, it can be seen that the first and the second upper lines T1 and T2 extending from the memory cell block formed over the sense amplifier are adjacent to the first and the second lower lines B1 and B2 extending from the memory cell block formed under the sense amplifier, respectively.
Coupling capacitance is generated between lines that form a BL sense amplifier. This may become a factor to deteriorate the performance of the BL sense amplifier that has to amplify a fine current. Furthermore, this coupling capacitance becomes more severe between lines that are extended from the same memory cell block.
In order to achieve a shield effect by solving this problem, an additional stable power line between the lines that form the BL sense amplifier are needed.
In order to insert the additional power line into the same area in addition to the lines of the BL sense amplifier, there is a burden on a process of further narrowing the width between the lines and a space into which the additional power line will be inserted is not sufficient according to an increase in the degree of integration of semiconductor devices.